The present invention relates generally to improvements in MOS (metal oxide semiconductor) memories, and in particular to a so-called "dummy cell" arrangement for sensing the logic state of a memory cell.
In MOS memories of the type considered herein, logical data is stored in a matrix of memory cells, each of which includes a cell capacitor for storing a charge which indicates whether its cell is in a logic 1 or a logic 0 state. A large number of such memory cells are typically associated with each of the memory's bit lines.
A number of "dummy cells" are also included in the memory. Each of these latter type of cells includes a dummy capacitor which is conventionally one-half the size of a memory cell capacitor and which is precharged to a reference voltage level. To sense the state of an addressed memory cell, the charge on the memory's cell capacitor is dumped on a first bit line and the charge on the dummy cell's capacitor is dumped on a second bit line. The resultant difference in voltage on the two bit lines is used as an indication of whether the memory cell is in a logic 1 or a logic 0 state.
A drawback of the conventional dummy cell arrangement described above is that, as memory cell capacitors are reduced in size, it is difficult to build a dummy cell capacitor which is one-half the size of the memory cell capacitor. Manufacturing variables which cause the size of a memory cell capacitor to vary by a given amount generally result in a similar change in the size of the dummy capacitor rather than one-half the change. Hence, their two-to-one size relationship changes.
For the foregoing reasons, conventional dummy cell arrangements become increasingly unreliable as the size of memory cell capacitors is reduced.